Post Register-Allocation Instruction Scheduling and Instruction Encodings


I have two questions I want to ask.
The first one, where is the post register allocation instruction scheduler function is called, and whether it could be called for both x86 and MIPS ?
The second question, is it possible to get the complete binary representation of some instruction (<= 32-bit binary encoding) for both x86 and MIPS in post register allocation instruction scheduler, and if yes how is that done ?

Jafar Jamal.