I would like to know if today in LLVM instruction predication can be used with instruction selection. I see that although we have the isPredicable flag for the TableGen instruction selection specs this flag seems it's not really used in the instruction selection pass.
I also know there is a method PredicateInstruction() (see http://llvm.org/docs/doxygen/html/classllvm_1_1TargetInstrInfo.html), that can be used on MachineInstr, after instruction selection and scheduling - examples of code where it is used are lib/CodeGen/IfConversion.cpp and ARM/Thumb2ITBlockPass.cpp.
Am I missing something?
I also found these emails on the list back from 2011:
- from http://lists.llvm.org/pipermail/llvm-dev/2011-May/040371.html:
"It's important to point out the current predication support is very limited. For example, the register allocator and instruction schedulers (and most of MI passes) are not predication aware. Also, only ARM uses the if-converter and it's done after register allocation.
There is quite a bit of infrastructure missing to make LLVM a fully predication aware compiler that's appropriate for an arch like IA64."
- from http://lists.llvm.org/pipermail/llvm-dev/2011-May/040329.html we have: "LLVM IR does not support predicated execution, so we need to match specific LLVM IR patterns into predicated instructions when compiling for PTX."