Prevent a intrinsic to be reordered?

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#1

Hello, I have an intrinsic that matches to a asm instruction directly. This intrinsic starts a coprocessor that can do anything.

If I put another instruction next to it (a multiplication for example), the “llc” reorders and puts the intrinsic after the multiplication.

I have tried all:

  • Setting the instruction like if it takes 256 cycles or 0 cycles.
  • Setting the instruction with “hasSideEffects” (which is ignored I think)
  • Setting the instruction as a load, branch, call, etc…
  • …

These later things are ignored, I don’t know if when the intrinsic is lowered, then it doesn’t matter (or perhaps the reorder is made before).

Any clues?

Thanks.
Julio

#2

Hello, Julio

These later things are ignored, I don't know if when the intrinsic is
lowered, then it doesn't matter (or perhaps the reorder is made
before).

What is the description of the instruction you're lowering intrinsic
into? Have you looked for the instruction flags defined in Target.td
file? You instruction should definitely have "isBarrier" flag set.

#3

Nothing… I’ll show you all the info related to:

The intrinsic: def int_soru_sre : Intrinsic<[llvm_void_ty, llvm_i32_ty], [IntrWriteMem]>;

The lower instruction (in MIPS):
class SORUI<bits<6> op, dag outs, dag ins, string asmstr, list pattern,
InstrItinClass itin>: FI<op, outs, ins, asmstr, pattern, itin>
{
let isBarrier = 1; // or call, hassideefects, …, nothing work
}

def SORU_SRE: SORUI<0b110011, (outs), (ins uimm16:$imm), “sre $imm”,
[(int_soru_sre imm:$imm)], IISoru>;

(With IISoru I made all the possible changes: a lot of cycles or none with all the functional units or none)

And an example:
tail call void @llvm.soru.sre( i32 5 )
mul i32 %b, %a ; :0 [#uses=1]

is coded as:

mult $2, $5, $4
sre 5

Best regards.
Julio

2008/9/14 Anton Korobeynikov <asl@math.spbu.ru>

#4

Does your instruction have a flag output?

Andrew

#5

Well, consider the multiply doesn’t touch memory and is independent on any outputs or side effects of llvm.soru.sre intrinsics, codegen is free to reorder the two. It may require llvm extension to model an instruction that has this level of side effects. One possible short term workaround is to move the intrinsic instruction into its own basic block. But they may not work if codegen prepare sink any instruction past it or when we switch to beyond basic block instruction selection.

Evan