prevents instruction-scheduler from interfereing instruction pair

Hi, LLVM list,

I am using Post-RA scheduler to reorder instructions. by now, it’s helpful for our processor but I meet a trouble. In our ISA, we have fixed instruction pairs. that is to say, our cpu must see instrA right before instrB. it’s not acceptable to have any instruction between them. we call it an instruction pair.

The problem is I am not aware of describing this kind of constraint in TD or cpp code. Post-RA scheduler may insert an instruction between instruction pair. Does any other ISA have similar constraints and how do you solve this problem? I know newer llvm has switched to MI-sched. I observed this same issue.

on my side, I defined some intrinsics which represent instruction pairs. Instruction-scheduler can not guarantee they appear consecutive in final instructions.

thanks,
–lx

What about describing the instruction pairs as pseudo-instructions, and then expanding them in a machine function pass at the pre-emit stage?

Amara

Amara,

first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing:
your approach is a little hacky, right? : )

// Expand pseudo instructions before second scheduling pass.
addPass(&ExpandPostRAPseudosID);
printAndVerify(“After ExpandPostRAPseudos”);

// Run pre-sched2 passes.
if (addPreSched2())
printAndVerify(“After PreSched2 passes”);

// Second pass scheduler.
if (getOptLevel() != CodeGenOpt::None) {
addPass(&PostRASchedulerID);
printAndVerify(“After PostRAScheduler”);
}

secondly, psuedo instruction is kind of compiler internal representation. I wish our instruction pair can disclose to programmer. intrinsics can do that.

thanks,
–lx

What I meant was to write your own expansion pass and run it after the
scheduler passes, e.g. in the pre-emit stage.

if (addPreEmitPass())

    printAndVerify("After PreEmit passes")

Though if it's too hacky for you then fair enough.

Amara

I think this after a second. I got your point. I can define a pseudo instruction for an instr-pair and expand it after post-RA-sched. as you said, in preEmitPass.

The original intrinsic can also be kept. I just convert the intrinsic to pseudo instruction in TargetLower. Thank you for your enlightening suggestion!

thanks,
–lx

I think this after a second. I got your point. I can define a pseudo instruction for an instr-pair and expand it after post-RA-sched. as you said, in preEmitPass.

The original intrinsic can also be kept. I just convert the intrinsic to pseudo instruction in TargetLower. Thank you for your enlightening suggestion!

FYI: If you did want to use the existing ExpandPostRAPseudo pass, then you could probably expand the pseudo into a bundle of machine instructions. See MIBundleBuilder. The PostRAScheduler schedules bundles as a single instructions.

-Andy