Problem in AMDGPU TableGen files

Yes, I can add a couple of lines of code to tgparser.cpp that will just check the types and complain if they aren't correct. I'll do that on Tuesday/Wednesday on Phabricator.

Are you also failing on RISCV, I see things that should fail.

For example, RISCVInstrInfoVSDPatterns.td contains

defm “” : VPatUSLoadStoreSDNodes;

Where AddrFI is a complex pattern, but VPatUSLoadStoreSDNodes is defined to take a RegisterClass.

multiclass VPatUSLoadStoreSDNodes {

RISCV isn't in my usual list of targets to build. There are a few backends I can't process due to this problem:

https://bugs.llvm.org/show_bug.cgi?id=48254

But I can get far enough to detect the issue at hand, so I will build every target over the next few days and post the list. I will also do what Simon Pilgrim suggested.