Problem with PostRASchedulerList.cpp - advice wanted

When you compile the attached file using

llc -march=x86 -mcpu=atom sched-bug.ll -o –

The Post-RA scheduler changes the sequence

movl %ecx, (%esp)

bsfl (%esp),%eax # this came from inline assembly code

to read

bsfl (%esp),%eax # this came from inline assembly code

movl %ecx, (%esp)

This is an incorrect schedule, because it seems the scheduler is not aware that the memory load by the bsfl depends on the memory store by the movl.

If you are familiar with the Post-RA scheduler works, then I would appreciate any suggestions you might have as to how I could fix this problem, such as by treating inline assembly code as a barrier or by including memory references in scheduling decisions.

Thanks,

Preston G

sched-bug.ll (234 Bytes)

Preston,

If it is not in itself obvious… With somewhat high degree of certainty you need to look at the scheduling DAG going into the Post-RA scheduler. If these two SUs do not have a chain edge between them, scheduler is free to reorder them.

Why they do not have an edge – it could be a number of reasons – from AA telling dag constructor so, to a bug in the dag construction logic. Hope this does not sound too trivial J

Sergei

Hi Preston,

Someone pointed me to a bug filed for this: http://llvm.org/PR13504.

Maybe you can add a memory clobber as a workaround.

-Andy