Problems with Verilator linting warning in Chisel generated code

oharboe · March 14, 2023, 11:58am

I’m getting a Verilator linting warning in LLVM CIRCT generated code.

If I change any line in this minimal test case, then the error goes away:

github.com/verilator/verilator

Why is "Latch inferred for signal" produced when linting the code below?

opened 11:53AM - 14 Mar 23 UTC

oharboe

new

With the ALU.sv code below, run: ``` $ verilator --version Verilator 4.218 …2022-01-17 rev v4.218 $ verilator --lint-only ALU.sv %Warning-LATCH: ALU.sv:11:3: Latch inferred for signal 'ALU.unnamedblk1.unnamedblk2._aluOutput_T_22' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 11 | always_comb begin | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/LATCH?v=4.218 ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to 1 warning(s) ``` ALU.sv: ```verilog module ALU( input clock, input [4:0] operation, input [63:0] inputs_1, inputs_0, inputs_2, input [16:0] immediate, output [63:0] output_0 ); reg [63:0] casez_tmp_1; always_comb begin automatic logic [63:0] lowHigh; casez (operation) 5'b00011: casez_tmp_1 = inputs_0 & inputs_1; 5'b00100: casez_tmp_1 = inputs_0 | inputs_1; 5'b00101: casez_tmp_1 = inputs_0 ^ inputs_1; 5'b01001: begin automatic logic [16:0] _aluOutput_T_22 = immediate >> {14'h0, inputs_2, inputs_1[0], inputs_0[0]}; casez_tmp_1 = {63'h0, _aluOutput_T_22[0]}; end default: casez_tmp_1 = inputs_0; endcase end endmodule ```

Is this an issue on the Verilator end or LLVM CIRCT end?

Or perhaps Chisel?

Chisel should not be able to articulate inferred latches, so inferred latches should not exist in Verilog generated from Chisel.

Cheers,