Problems with Verilator linting warning in Chisel generated code

I’m getting a Verilator linting warning in LLVM CIRCT generated code.

If I change any line in this minimal test case, then the error goes away:

Is this an issue on the Verilator end or LLVM CIRCT end?

Or perhaps Chisel?

Chisel should not be able to articulate inferred latches, so inferred latches should not exist in Verilog generated from Chisel.