PrologEpilogProblems;

After PrologEpilogCodeInserter I found that the instructions that restore callee saved registers S0,S1,LR are in the wrong location ,the instructions are:
%S0 = LD %SP, 36; mem:LD4[FixedStack2]
%S1 = LD %SP, 40; mem:LD4[FixedStack1]
%LR = LD %SP, 44; mem:LD4[FixedStack0]
(LR is the Return address register)
the whole code of print-machineinstrs are:

After PrologEpilogCodeInserter:

Machine code for function L_mpy_ls: Post SSA

BB#0: derived from LLVM BB %0
Live Ins: %LR %S1 %S0
%SP = ADDI %SP, -48
PROLOG_LABEL <MCSym=_tmp0>
ST %LR, %SP, 44; mem:ST4[FixedStack0]
ST %S1, %SP, 40; mem:ST4[FixedStack1]
ST %S0, %SP, 36; mem:ST4[FixedStack2]
PROLOG_LABEL <MCSym=_tmp1>
%S0 = LD %SP, 48; mem:LD4FixedStack-1
ST %S0, %SP, 0; mem:ST4FixedStack-4
JSUB ga:extract_l, , %LR, %SP, %V0
%V1 = ADDI %ZERO, 1
ST %V0, %SP, 0; mem:ST4FixedStack-5
ST %V1, %SP, 4; mem:ST4[FixedStack-6]
JSUB ga:shr, , %LR, %SP, %V0
%S1 = LD %SP, 52; mem:LD4[FixedStack-2]
%V1 = LIL 32767
%V0 = AND %V0, %V1
ST %V0, %SP, 4; mem:ST4[FixedStack-8]
ST %S1, %SP, 0; mem:ST4FixedStack-7
JSUB ga:L_mult, , %LR, %SP, %V0
%V1 = ADDI %ZERO, 15
ST %V0, %SP, 0; mem:ST4FixedStack-9
ST %V1, %SP, 4; mem:ST4[FixedStack-10]
JSUB ga:L_shr, , %LR, %SP, %V0
ST %S0, %SP, 0; mem:ST4FixedStack-11
%S0 = COPY %V0
JSUB ga:extract_h, , %LR, %SP, %V0
ST %S0, %SP, 0; mem:ST4FixedStack-12
ST %S1, %SP, 4; mem:ST4[FixedStack-13]
ST %V0, %SP, 8; mem:ST4FixedStack-14
%S0 = LD %SP, 36; mem:LD4[FixedStack2]
%S1 = LD %SP, 40; mem:LD4[FixedStack1]
%LR = LD %SP, 44; mem:LD4[FixedStack0]
JSUB ga:L_mac, , %LR, %SP, %V0
%SP = ADDI %SP, 48
RetLR %V0

what I want to get is :

JSUB ga:extract_h, , %LR, %SP, %V0
ST %S0, %SP, 0; mem:ST4FixedStack-12
ST %S1, %SP, 4; mem:ST4[FixedStack-13]
ST %V0, %SP, 8; mem:ST4FixedStack-14
JSUB ga:L_mac, , %LR, %SP, %V0

%S0 = LD %SP, 36; mem:LD4[FixedStack2]
%S1 = LD %SP, 40; mem:LD4[FixedStack1]
%LR = LD %SP, 44; mem:LD4[FixedStack0]

%SP = ADDI %SP, 48
RetLR %V0

can you tell me the problem? Thank you!