question about flag register through instruction selection and instruction scheduling


I am trying to support addition of int64 on my target which has only 32 bit registers.
The target has only normal add instruction which adds two 32 bit register, writes result to a register, and updates carry flag in flag regitser.
It does not have the addwithcarry instruction which adds two register and carry flag, writes result to a register, and updates carry flag.

I have refered to the implementation of 64bit addition on cortex-a7 which is arm architecture and have some questions.
the c source, .ll file, and debug dump is attached.
-----------------------------------------debug dump-------------------------------------------------------------

1522Optimized legalized selection DAG: %bb.0 ‘foo:entry’
1523SelectionDAG has 16 nodes:
1524 t0: ch = EntryToken
1525 t17: ch,glue = CopyToReg t0, Register:i32 $r0, t29
1526 t8: i32,ch = CopyFromReg t0, Register:i32 %3
1527 t4: i32,ch = CopyFromReg t0, Register:i32 %1
1528 t25: i32,i32 = ARMISD::ADDE t8, t4, t29:1
1529 t19: ch,glue = CopyToReg t17, Register:i32 $r1, t25, t17:1
1530 t6: i32,ch = CopyFromReg t0, Register:i32 %2
1531 t2: i32,ch = CopyFromReg t0, Register:i32 %0
1532 t29: i32,i32 = ARMISD::ADDC t6, t2
1533 t20: ch = ARMISD::RET_FLAG t19, Register:i32 $r0, Register:i32 $r1, t19:1

test.arm.debug (87.4 KB)

test.arm.ll (1.35 KB)

test.c (62 Bytes)