Question about quad-register

Hi All,

  If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit
register), is it possible mapping quad-register
to v4i32 so that the following example work?

    typedef int v4si __attribute__ ((vector_size (16)));

    void foo(v4si i) {
      v4si j = i;

I don't know how to write to represent the concept of
occupying quad-register R0:R1:R2:R3
once seeing v4i32. Any example that I can refer to?



The standard trick is to define the "quad register" that would alias
r0/r1/r2/r3. See e.g. ARM backend.

Hi Anton,

  I guess you mean something like this in

    def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64,
v2f32, v4f16], 64,
                                             (sequence "D%u", 0, 31)> {

    def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2],
                                                            [(shl DPR, 0),
                                                             (shl DPR, 2)]>;

or this?

  let SubRegIndices = [dsub_0, dsub_1] in {
    def Q0 : ARMReg< 0, "q0", [D0, D1]>;
    def Q1 : ARMReg< 1, "q1", [D2, D3]>;