Question about store with unaligned memory address

Hi All,

I have a question about store with unaligned memory address.

I am working on target which has only 4 byte aligned load and store instruction and I am generating 2 load and store instructions to store value on memory which the address is not aligned 4. I am doing it with lowering store as follow:

1. make low and high address with alignment.
2. load 2 words from low and high address.
3. manipulate them with values to store according to alignment.
4. store 2 words modified to low and high address

There could be independent stores with same target memory address because it makes and accesses low and high address with lowering. In order to keep the order between loads and stores, I have used chain and glue on the DAG but some passes have mixed it in machine instruction level. I am feeling above idea is not good... Do I need to use pseudo instruction? I am not sure which one is good idea... Could someone have experience with unaligned memory access? If I missed something, please let me know. It will be really helpful!!!

Thanks,
JinGu Kang

I am doing it with lowering store as follow:

1. make low and high address with alignment.
2. load 2 words from low and high address.
3. manipulate them with values to store according to alignment.
4. store 2 words modified to low and high address

Sounds ok.

In order to keep the order between loads and stores, I have used chain and
glue on the DAG but some passes have mixed it in machine instruction level.

Glue isn't necessary, chains are sufficient.

I'm not sure what pass reordered dependent loads and stores, but that sounds bad. What matters in cases like this are the MachineMemOperands. If there isn't any on a load/store instruction, it should be treated conservatively (i.e. alias everything else), if there is one, it'd better be correct. Wrong MMO could certainly lead to such behavior.

-Krzysztof

Hi Krzysztof,

Thanks for response.

The method is working almost of test cases which use load and store
instructions connected with chain. There is other situation. Let's
look at a example as follows:

typedef unsigned short int UV __attribute__((vector_size (8)));

void test (UV *x, UV *y) {
  *x = *y / ((UV) { 4, 4, 4, 4 });
}

The target does not support vector type so CodeGen tries to split and
scalarize vector to legalize type. While legalizing vector type, the
stores of each vector elements nodes are generated from
'DAGTypeLegalizer::SplitVecOp_STORE'. But the stores are not connected
with chain. I guess it assumes each vector element's address is
different. The each store is lowered to load and store nodes with high
and low address but they are not connected with the other store's one.
It causes problem. I am not sure how to solve this situation
correctly.

Thanks,
JinGu Kang

I’m not clear, but it sounds like maybe your issue is not just alignment, but that you have no 1/2-byte load or store operations at all on your target?

Do you mean that to do any 2-byte store, even if it’s naturally aligned, you need to load the 4-byte word that contains it, replace the low or high half as appropriate, and then use a 4-byte store to store back the modified value?

I think I need to explain the situation more. There is a example from
previous example.

Source code:
typedef unsigned short int UV __attribute__((vector_size (8)));

void test (UV *x, UV *y) {
  *x = *y / ((UV) { 4, 4, 4, 4 });
}

IR snippet from "*x = ...":
...
  %div = udiv <4 x i16> %1, %2
  %3 = load <4 x i16>*, <4 x i16>** %x.addr, align 4
  store <4 x i16> %div, <4 x i16>* %3, align 8
...

Selection Dag before type legalize:
...
  0x85ceac8: i32,ch = load 0x85ced18, 0x85cf1b8,
0x85c8e20<LD4[%x.addr]> [ORD=12]
...
        0x85d3a28: v4i16 = srl 0x85d51a0, 0x85c79d0 [ORD=11] <-- from udiv
      0x85c8aa8: ch = store 0x85ceac8:1, 0x85d3a28, 0x85ceac8,
0x85c8e20<ST8[%3]> [ORD=13]
...

Selection Dag after type legalize:
...
0x85ceac8: i32,ch = load 0x85d0798, 0x85cf1b8, 0x85c8e20<LD4[%x.addr]>
[ORD=12] [ID=-3]
...
          0x85dc2a8: ch = store 0x85ceac8:1, 0x85d18c8, 0x85ceac8,
0x85c8e20<ST2[%3](align=8), trunc to i16> [ORD=13] [ID=-3]
...
          0x85dc058: ch = store 0x85ceac8:1, 0x85c8cf8, 0x85dbab0,
0x85c8e20<ST2[%3(align=8)+2](align=2), trunc to i16> [ORD=13] [ID=-3]
...
          0x85db860: ch = store 0x85ceac8:1, 0x85d2fc0, 0x85dacd0,
0x85c8e20<ST2[%3(align=8)+4](align=4), trunc to i16> [ORD=13] [ID=-3]
...
         0x85db610: ch = store 0x85ceac8:1, 0x85d09e8, 0x85db170,
0x85c8e20<ST2[%3(align=8)+6](align=2), trunc to i16> [ORD=13] [ID=-3]
...

The vector type operations are scalarized because the target does not
support vector type like above selection dag. The scalarized each
store has the same chain from load:0x85ceac8 because it assumes they
access different address. As I said on first e-mail, I lower the each
store to 2 load and 2 store nodes for 2 words with high and low
address and the address could be same between adjacent vector
element's stores. In SelectionDAG stage, I have tried to keep the
order of load and store nodes with chain and glue while I lowering the
each element's store. But, In machine IR stage, it is broken because
they are not dependent each other and could access same address. One
vector element's load and store could interfere between the other's
load and store. If I try to use the 2 words way, I need to keep the
each vector element's store as one chunk. But I am not sure whether it
is good way or not... If someone has experience with this kind of
situation, please give me any comment. It will be very helpful.

Thanks,
JInGu Kang

Hi James,

Thanks for response.

you have no 1/2-byte load or store operations at all on your target?

Yep, it only has 4 byte load and store.

even if it's naturally aligned, you need to load the 4-byte word that contains it, replace the low or high half as appropriate, and then use a 4-byte store to store back the modified value?

Yep, I am doing it.

I have written the situation a little bit more with selection dag
snippet a short time ago. Please reference it.

Thanks,
JinGu Kang

In fact this is a pretty bad legalizing/lowering because you only need to load and edit for the first and last values in the vector. The other words are completely replaced and don’t need to be loaded at all.

I think you need to legalize differently when it is not aligned.

Hi Bruce,

Thanks for response.

I also think it is not good way. Do you have the other ways to legalize it?

Thanks,
JinGu Kang

I’m afraid I’m not yet skilled with LLVL IR, but I think you’d probably want to do something like this:

#include <stdint.h>

typedef uint32_t elt;
typedef elt v4 attribute ((vector_size (16)));

void store(v4 *p, v4 v){
uintptr_t align = uintptr_t(p) & (sizeof(elt)-1);
if (align == 0){
*p = v;
} else {
// assert sizeof(elt) == 4
// assert align == 2
elt base = (elt)(uintptr_t(p) - 2);
elt lomask = (1<<16)-1;
elt himask = ~lomask;
base[0] = (base[0] & lomask) | v[0] << 16;
base[1] = v[0] >> 16 | v[1] << 16;
base[2] = v[1] >> 16 | v[2] << 16;
base[3] = v[2] >> 16 | v[3] << 16;
base[4] = v[3] >> 16 | (base[4] & himask);
}
}

Of course you’ll want to convert one LLVM IR to another, not actually insert C code, but you can compile this code and see what IR is produced.

Interestingly, LLVM manages to optimize this to one elt load, one elt store, and an aligned vector store. Plus some in-registers shuffling, of course.

Sorry … two elt loads, one elt store, and an aligned vector store.

Hi Bruce,

Thanks for response.

I think you mean custom lowering of vector type store using algorithm
you mention . It can avoid the situation as I mentioned on previous
e-mail. But I am not 100% sure whether the only vector store generates
unchained stores. I have seen 'getMemcpyLoadsAndStores' also generates
them. It can also be avoided with something like 'MaxStoresPerMemcpy =
0'. I wanted to solve the problem in each store level like lowering
store or making pseudo machine instruction.

Thanks,
JinGu Kang