Question about TableGen RegisterClass definition

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1

Hi All,

I have a question about TableGen RegisterClass definition.

I need to map different size of MVTs into a register class as below.

def TestReg : RegisterClass<“Test”, [v8i32, v4i32], …>

When I look at TableGen and CodeGen, it looks the types are used as following:

  1. MCRegisterClass’s RegSize and Alignment
  2. SpillSize in TableGen
  3. Type constraint for instruction pattern matching

From my opinion, it seems it is possible to do it… but I am not 100% sure… If anyone has information about it, please give me comment.

Thanks

2

Ping!

I would like to check whether we can map multiple MVTs with different size to one register class as below.

def TestReg : RegisterClass<“Test”, [v32i16, v32i32], …>

The register classes could be used as below.

def : Pat<(v32i16 (add TestRegs:$src0, TestRegs:$src1)),

(vaddv32i16 $src0, $src1)>;

def : Pat<(v32i32 (add TestRegs:$src0, TestRegs:$src1)),

(vaddv32i32 $src0, $src1)>;

Is it possible to implement above register class and pattern? I could create different register class per each MVT with different size… but it is not preferred internally… If anyone has information about above one, please share it.

Thanks

JinGu Kang

3

Sorry… I made a mistake from below definition.

def TestReg : RegisterClass<“Test”, [v32i16, v32i32], …>

—>
def TestReg : RegisterClass<“Test”, [v32i32, v32i16], …>

TableGen takes the size of register class from first type on the type list. In this case, the bigger size is correct.

Thanks
JinGu Kang