Hi,
I am trying to do a backend to a very simple microcontroller. I have some
questions.
1) I have instruction which do "r1 <- r1 op r2", from what I have ssen I
must declare them like:
let isTwoAddress = 1 in
def ADD : FopRR< 0b01010,
(outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY),
"ADD $sX, $sY"),
[(set CPURegs:$sX, (add CPURegs:$isX, CPURegs:$sY))]>;
Where CPURegs is my class of register. I suppose that the pass
TwoAddressInstructionPass will make the $sX and $isX register the same (it
unify the out reg and the first in reg?) ?
When should I set isConvertibleToThreeAddress to 1? When I have another form
of the instruction which take a three addresses?
2) Instr class contain the following properties. I suppose they must be set
correctly for? I have some question on them. If only '?' I don't understand
at all, if no comment then I think I understand.
int CodeSize = 0; // in bits? Or bytes?
int AddedComplexity = 0; // ?
bit isReturn = 0;
bit isBranch = 0;
bit isIndirectBranch = 0;
bit isBarrier = 0; // ? memory barrier?
bit isCall = 0;
bit isSimpleLoad = 0; // simple?
bit mayLoad = 0;
bit mayStore = 0;
bit isTwoAddress = 0; // see question 1
bit isConvertibleToThreeAddress = 0; // see question 1
bit isCommutable = 0; // see rq1 below
bit isTerminator = 0; // terminate what? A BB, A function, or the
program
bit isReMaterializable = 0; // ?
bit isPredicable = 0;
bit hasDelaySlot = 0;
bit usesCustomDAGSchedInserter = 0;
bit hasCtrlDep = 0; // ?
bit isNotDuplicable = 0; // ?
bit hasSideEffects = 0;
bit mayHaveSideEffects = 0; // how is this different from has side effect?
bit neverHasSideEffects = 1;
Rq1: If I have a instruction 'add reg, imm' and don't have 'add imm, reg' I
suppose the instruction isn't commutable?
3) For conditional jump:
the architecture use the flags carry and zero to do conditional jump (ex:
jump if carry set) and most arithmetic operation set these flags. I was
wondering how to handle this. I have seen some CC (condition code) in some
backend but it is not clear. Or I could model precisely the flag but then
the operations would have more than on output and it seems this isn't
supported at least in the tablegen? Could you give me some pointer
4) IO: on this µC, the IO aren't mapped in the main address space and use a
separate set of load/store. I was thinking of using the new functionality of
multiple address space. But should the separation be done in the
legalization phase or in the instruction selection phase?
This is all for the moment 
Regards,