Re-computing Live-in/Live-out Physical Registers for Basic Blocks Using LivePhysRegs

Thank you for your reply!

If liveness of APSR is not tracked, how does the code generator determine whether instructions like cmp are dead code or not?
Is it true that, for every use of APSR (such as a conditional branch), the used def (such as cmp, add, etc.) is always in the same basic block?
Is it true that APSR is never assumed to live across basic block boundaries?

Thank you!

Ming Zhang

It looks like LLVM uses the CPSR register to model compares and conditional jumps. (I recommend writing some test programs and using -print-machineinstrs to experiment yourself). APSR seems to be just a different name/alias for some of the CPSR flags (including the NZCV used for conditional branching).

- Matthias

I have tried to build MC instructions using MCInstBuilder.
It does model APSR using CPSR. Adding ARM::APSR as a register operand would trigger an assertion failure. When I use ARM::CPSR in place of ARM::APSR, the instructions in the generated native assembly code use APSR as desired.

For my control flow checking instrumentation, I would like to minimize overhead of additional instrumentation code inserted into the program code.
The instrumentation code may clobber APSR. I would like to use liveness information of APSR to decide whether APSR needs to be saved or not for every instrumentation code snippet.
If tracking liveness of APSR/CPSR is difficult, I may consider generating instrumentation code that does not clobber it.

Thank you!