Register allocation limitations

Project Infrastructure LLVM Dev List Archives
#1

Hi all.

if there is limitation for the registers to be used together in an
instruction, should i try to change it in the register allocation pass
or should i try it somewhere else??

example.

lets say we have to add 2 registers

addu rx ,ry ,rz

there is a limitation that says that the two regs that will be added they
can not have the same mod4
so we can add r1 , r2 but cannot add r1,r5.

thanks
Stavropoulos Nikos

#2

``Hi Nikos,

You can model your requirement in the *.td using RegisterClass as

def SrcRegs : RegisterClass<“Src”, [i32], 4,
(add R0, R2, R4, R6
)>;

def DstRegs : RegisterClass<“Dst”, [i32], 4,
(add R1, R3, R5, R7
)>;

Thanks
~Umesh

#3

Hi Umesh,

thanks for answering.
i think i did not describe the problem well enough.
i have no problem with the register that should be written.
lets say we have a madd instruction
madd D, R, S, T.
D : don't care
R : lets say it is R4
S : should be whatever register that has different mod(register,4) != 0 so
lets pick R7
T: should be whatever register that has different mod(register,4) != 0
(because of R) and
     should be whatever register that has different mod(register,4) != 3
(because of S) so we have to pick someone
     with mod 1 or 2 so we can choose R5

is there a way to do it somehow without declaring different register
classes, some dynamic kind way?