My target has special requirements during register allocation - there is both a need to handle register pairing and to never spill a flag result reg-class (which might happen at -O0 for no obvious reason).
Since neither of these issues seems to be supported, I have tried to pre-allocate these registers in the preRA pass. This has resulted in “using undefined physical register” verification failure with the fast regalloc, as this regalloc does not scan the code properly for used pregs, and thus marks a use-physreg-op as ‘Kill’ when it is in fact used in the following instruction (where it was marked with ‘Kill’).
It seems that the other register allocators are fine with pre-allocation, as they scan for preg live ranges, right?
I wonder, is there a way to know wich regalloc is loaded by the passmanager in the preRA-pass?
(In GCC, there is a way to specify register pairing on the primitive level, by adding predicates for operand-combinations, eg “base1, base2, base3” for addr-reg, and “offs1-2, offs3-4, offs5-6” for the index register. Is there a neat way of doing this with Tablegen? For each instruction with two paired register operands, these combinations must be the only legal ones, but do I have to write several instruction definitions to express this?)
To do away with pre-allocation, LLVM would have to be extended with an RegClass/register-attribute ‘spillable’, and a register allocator would have to implement register pairing. That would be PBQP, right? What’s your standpoint on these extensions? I would be glad to work with you on this, when I have the time.