Register classes and FP64 on target with no FP64 support

Hi LLVM-Dev,

I am trying to implement support for emulated FP64 on our target. Many operations work fine, invoking the appropriate helper function in ‘compiler-rt’. But we don’t have a specific register class for FP64 and LLVM usually selects a pair of 32-bit integers, which is fine. The problem is that it doesn’t “always” select a pair of 32-bit integers, and then I get an assertion in ‘TargetRegisterInfo::getMinimalPhysRegClass’ that says “Couldn’t find the register class”.

The funny thing is that something like ‘a = b * c;’ works perfectly, but the much simple ‘a = b;’ causes this assertion.

We have not used ‘setOperationAction’ for any of the FP64 operations, nor have we created a special register class for them either, in the expectation that it would just reduce to the underlying integers and ‘compiler-rt’ calls.

I’m a bit stumped, so does anyone have any advice about how I should describe our target so that it supports emulated FP64 using either a pair of 32-bit integers or a single 64-bit register as the underlying implementation type?


MartinO - Movidius