I'm trying to implement a simplified X86_64 architecture targeting backend for LLVM. While I have figured that I can introduce the intended architecture as a subtarget of X86 in X86.td, what i don't understand is how the registers specified in X86RegisterInfo.td and the ISA in X86InstrInfo.td are correlated with each sub-architecture. Where are the correlations defined? The simplifications I'm trying to make are:
1. No registers smaller than 64 bit
2. All instructions are 64 bit in length
3. No FPU instructions (this is covered by not including the SSE feature when defining the subtarget I guess?)
4. Minimal ISA (need to arrive at the smallest subset of instructions that will allow me to still compile something like nginx. While this is something that will involve quite a bit of trial and error, I don't know where to figure out what subtarget picks up which instructions and registers)
Would it be easier for me to create a new target and copy the X86 files into it and start deleting things I want to get rid of?