We are proposing the integration of a new backend targeting the LoongArch ISA.
- LoongArch intro
LoongArch is a RISC style ISA which is independently designed by Loongson
Technology in China. It is divided into two versions, the 32-bit version (LA32)
and the 64-bit version (LA64). LA64 applications have application-level
backward binary compatibility with LA32 applications. LoongArch is composed of
a basic part (Loongson Base) and an expanded part. The expansion part includes
Loongson Binary Translation (LBT), Loongson VirtualiZation (LVZ), Loongson SIMD
EXtension (LSX) and Loongson Advanced SIMD EXtension(LASX).
Currently the LA464 processor core supports LoongArch ISA and the Loongson
3A5000 processor integrates 4 64-bit LA464 cores. LA464 is a four-issue 64-bit
high-performance processor core. It can be used as a single core for high-end
embedded and desktop applications, or as a basic processor core to form an
on-chip multi-core system for server and high-performance machine applications.
- Conform to the policy
According to https://llvm.org/docs/DeveloperPolicy.html#adding-a-new-target
a) Of couse it will be an experimental target at first.
b) I’d like to be the code owner of this target.
c) There is an active community behind the target: https://github.com/loongson
And we will provide builbot support.
- More docs can be found at:
We started to implement an out-of-tree LoongArch LLVM port since last year
based on llvm-8/11 and posted it to https://github.com/loongson/llvm-project
last month. This port also adds supports to clang front-end and we finally pass
100% llvm-test-suite in O0/1/2/3 optimization levels. But in this port there
are a few issues we must handle to get it upstreamed.
- The codebase is too old that means we may use some out-of-date interfaces.
- The test coverage is not broad enough.
- Coding standard is not met.
So we decide to refactor this port base on llvm trunk and integrate to upstream
incrementally. This approach of small, incremental patches is somewhat similar
to what has been or is being done with many other backends like RISC-V, CSKY
The current status is that we have completed a series of 5 patches adding
triple, ELF machine, basic interger instructions and registers definition. We
will submit them for review later. Any comments are welcome and please do let
me know if you’d like to be added as a reviewer to future patches.
A rough development roadmap:
- MC layer
- CodeGen for Loongson Base
- CodeGen for ISA extensions, including LSX and LASX
- Support clang
- Support other sub-projects