I'd like to add HLE support in LLVM/clang consistent to GCC's style . HLE from Intel TSX  is legacy compatible instruction set extension to
specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order
flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for target-specific memory model, bit 15-0 for the general memory model.) To follow the similar approach, I propose to
change LLVM/clang by adding:
+ a metadata 'targetflags' in LLVM atomic IR to pass this
target-specific memory model hint
+ one extra target flag in AtomicSDNode & MemIntrinsicSDNode to specify XACQUIRE or XRELEASE hints
This extra target flag is embedded into the SubclassData fields. The following is rationale how such target flags are embedded into SubclassData in SDNode
here is the current SDNode class hierarchy of memory related nodes
SDNode -> MemSDNode -> LSBaseNode -> LoadSDNode
> + -> StoreSDNode
+ -> AtomicSDNode
+ -> MemIntrinsicSDNode
here is the current SubclassData definitions:
bit 0~1 : extension type used in LoadSDNode
bit 0 : truncating store in StoreSDNode
bit 2~4 : addressing mode in LSBaseNode
bit 5 : volatile bit in MemSDNode
bit 6 : non-temporal bit in MemSDNode
bit 7 : invariant bit in MemSDNode
bit 8~11: memory order in AtomicSDNode
bit 12 : synch scope in AtomicSDNode
Considering the class hierarchy, we could safely reused bit 0~1 as the target flags in AtomicSDNode/MemIntrinsicNode
+ X86 backend is modified to generate additional XACQUIRE/XRELEASE prefix based on the specified target flag
The following are details of each patch:
This patch adds 'targetflags' support in AtomicSDNode and MemIntrinsicSDNode. It will check metadata 'targetflags' and embedded its value into SubclassData. Currently, only two bits are defined.
This patch adds HLE feature and auto-detection support
This patch adds XACQUIRE/XRELEASE prefix and its assembler/encoding support
This patch enables HLE code generation by extending the current logic to handle 'targetflags'.
This patch adds target flags support in __atomic_* builtins. It splits the whole 32-bit order word into high and low 16-bit parts. The low 16-bit is the original memory order and the high 16-bit will be re-defined as target-specific flags and passed through 'targetflags' metadata.
It adds '-m[no]hle' option to turn on HLE feature or not. Once HLE feature is turned on, two more macros (__ATOMIC_HLE_ACQUIRE and __ATOMIC_HLE_RELEASE) are defined for developers to mark atomic builtins.
Thanks for your time to review!
0002-Add-HLE-target-feature.patch (3.77 KB)
0004-Enable-HLE-code-generation.patch (56.8 KB)