[RFC] ASM Goto With Output Constraints

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What about SelectionDAG representation? Currently we expand callbr to INLINEASM_BR and BR. Both of which are terminators. But in order to support outputs we would need to put CopyFromReg nodes between them.

Generally, I’d prefer if we didn’t keep designing new features that assume the programmer knows what they’re doing. Personally, I had been considering reworking LLVM’s Windows EH representation to eliminate the catchswith instruction, which just exists to multiplex invoke unwind edges to multiple catch blocks. Instead, we’d use callbr, and I had been assuming it would have the normal behavior of producing the return value only along the normal path.

Do you think landingpad offers alternative inspiration for how to handle this? i.e. you could have a special EHPad-like instruction (must be first non-PHI instruction) that produces a value along abnormal paths.

Is there a reason why callbr needs to be lowered to INLINEASM_BR and not a normal INLINEASM?

-bw

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

It’d sure be a whole lot easier to not have the values valid on the secondary exit blocks. Can you present examples where preserving the values on the branches is be a requirement? (I feel like I’ve seen some before, but it’d be good to be reminded).

E.g., imagine code like this:

<<
entry:
br i1 %cmp, label %true, label %false
true:
%0 = callbr { i32, i32 } asm sideeffect “poetry $0, $1”, “={r8},={r9},X” (i8* blockaddress(@vogon, %error)) to label %asm.fallthrough [label %error]

false:

%1 = callbr { i32, i32 } asm sideeffect “poetry2 $0, $1”, “={r10},={r11},X” (i8* blockaddress(@vogon, %error)) to label %asm.fallthrough [label %error]

error:
%vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

Normally, if a common register cannot be found to use across relevant block transitions, it can simply fall back on storing values on the stack. But, that’s not possible with callbr, since the location is fixed by the asm, and no code can be inserted after the values are written, before the branch (as both value writes and the branch are inside the asm blob). So what can be done, in that case?

One thing you might be able to do is to duplicate the error block so you have a different target for every callbr, but I’d consider that an invalid transform (because the address of the block is potentially being used as a value in the asm too).

Another thing you could perhaps do is reify the source-block-number as an actual value – storing a “1” before the callbr in true, and storing a “2” before the callbr in “false”. Then conditional-branch based on that…but that’s real ugly…

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:2:30: error: ‘asm goto’ cannot have output constraints
asm goto(“poetry %0, %1” : “=r”(a), “=r”(b) : : : error);

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  • |

However, LLVM doesn’t restrict control transfer instructions from having outputs (e.g. the invoke instruction). We propose changing LLVM’s callbr instruction to allow return values, similar to how LLVM’s implementation of inline assembly (via the call instruction) allows return values. Since there can potentially be zero to many output constraints, callbr would now return an aggregate which contains an element for each output constraint. These values would then be extracted via extractvalue. With our proposal, the above C example will be converted to LLVM IR like this:



define i32 @vogon(i32 %a, i32 %b) {
entry:
%0 = callbr { i32, i32 } asm sideeffect “poetry $0, $1”, “=r,=r,X”
(i8* blockaddress(@vogon, %error))
to label %asm.fallthrough [label %error]




asm.fallthrough:
%asmresult.a = extractvalue { i32, i32 } %0, 0
%asmresult.b = extractvalue { i32, i32 } %0, 1
%result = add i32 %asmresult.a, %asmresult.b
ret i32 %result

error:
ret i32 -1
}

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Note that unlike the invoke instruction, callbr’s return values are assumed valid on all branches. The assumption is that the programmer knows what their inline assembly is doing and where its output constraints are valid. If the value isn’t valid on a particular branch but is used there anyway, then the result is a poison value. (Also, if a callbr’s return values affect a branch, it will be handled similarly to the invoke instruction’s implementation.) Here’s an example of how this would work:

Generally, I’d prefer if we didn’t keep designing new features that assume the programmer knows what they’re doing. Personally, I had been considering reworking LLVM’s Windows EH representation to eliminate the catchswith instruction, which just exists to multiplex invoke unwind edges to multiple catch blocks. Instead, we’d use callbr, and I had been assuming it would have the normal behavior of producing the return value only along the normal path.

Wouldn’t it be unnecessarily restrictive though to limit the valid return values only to the normal edge? (This is more for the generality of the callbr instruction and not necessarily related to the initial inspiration for “asm goto”.)

Do you think landingpad offers alternative inspiration for how to handle this? i.e. you could have a special EHPad-like instruction (must be first non-PHI instruction) that produces a value along abnormal paths.

I haven’t touched EH stuff for awhile so things have probably changed. It’s an intriguing notion and may help alleviate the issues James mentioned. Could you write some pseudo-IR to show more what you’re thinking?

-bw

This was Chandler’s proposal after observing the number of places I had to update in MachinePasses to understand the control flow change happening in the middle of the basic block. He thought just making it a terminator would make it simpler.

There is some special casing of exception handling in MachineIR passes to make the control flow for invoke work. Look for isEHPad() or hasEHPadSuccessor()

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how “the programmer knows what they’re doing”. Perhaps I’m being too cavalier here? My concern, if you want to call it that, is that we don’t be too restrictive on the new behavior. For example, the “asm goto” may set a register to an error value (made up on the spot; may not be a common use). But, if there’s no real reason to have the value be valid on the abnormal path, then sure we can declare that it’s not valid on the abnormal path.

I see. I can think of a couple of ways to handle this, but they fall into the hacky category. It may just be that we need to bite the bullet and update all of the places in the MachinePasses. :frowning: Could you point to the comments made by you and Chandler? I’d like to familiarize myself with them.

-bw

What about SelectionDAG representation? Currently we expand callbr to INLINEASM_BR and BR. Both of which are terminators. But in order to support outputs we would need to put CopyFromReg nodes between them.

Or maybe we should support having terminators that define values? People ask about this from time to time, and that seems like the higher-overall-value extension to make to the MI representation.

-Hal

~Craig

...

I believe at least some portion of the INLINEASM_BR decision is discussed here https://reviews.llvm.org/D53765?id=184024#inline-508610 Anything that’s on record anywhere should be in that review. I may have had some conversations with Chandler on IRC, but I’m not sure.

~Craig

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how “the programmer knows what they’re doing”. Perhaps I’m being too cavalier here? My concern, if you want to call it that, is that we don’t be too restrictive on the new behavior. For example, the “asm goto” may set a register to an error value (made up on the spot; may not be a common use). But, if there’s no real reason to have the value be valid on the abnormal path, then sure we can declare that it’s not valid on the abnormal path.

I think I should explain my “programmer knows what they’re doing” statement a bit better. I’m specifically referring to inline asm here. The more general “callbr” case may still need to be considered (see Reid’s reply).

When a programmer uses inline asm, they’re implicitly telling the compiler that they do know what they’re doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. “cpuid”) or the compiler isn’t able to give them the needed performance in a critical section. I’m extending this sentiment to callbr with output constraints. Let’s take your example below and write it as “normal” asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
br i1 %cmp, label %true, label %false

true:

%0 = call { i32, i32 } asm sideeffect “poetry $0, $1”, “={r8},={r9}” ()

br label %end

false:

%1 = call { i32, i32 } asm sideeffect “poetry2 $0, $1”, “={r10},={r11}” ()
br label %end

end:
%vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever’s done today for “normal” inline asm is what I think should be the behavior for the inline asm callbr variant. If this doesn’t seem sensible (and I realize that I may be thinking of an “in a perfect world” scenario), then we’ll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

-bw

I guess distinguishing between callbr and asm goto is reasonable. We can tolerate optionally initialized outputs for inline asm. It’s just the same as having an output constraint register that you forget to write in the asm blob. However, it would be good if callbr had some way to represent whether the returned value is alive along any particular outgoing edge.

I mentioned that we could look to landingpad for inspiration here. I mention it because it is, essentially, the alternate exceptional return value of a possibly throwing call. The values it produces are carried in the usual X86 return registers, RAX:RDX, so they really are kind of an alternate return value. However, with asm goto, it’s not possible to have different output constraints along different edges, so after thinking about it some more, I think this is overkill. It’s just one way we could implement that live value indication, and I think it’s probably not as good as changing callbr itself.

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how “the programmer knows what they’re doing”. Perhaps I’m being too cavalier here? My concern, if you want to call it that, is that we don’t be too restrictive on the new behavior. For example, the “asm goto” may set a register to an error value (made up on the spot; may not be a common use). But, if there’s no real reason to have the value be valid on the abnormal path, then sure we can declare that it’s not valid on the abnormal path.

I think I should explain my “programmer knows what they’re doing” statement a bit better. I’m specifically referring to inline asm here. The more general “callbr” case may still need to be considered (see Reid’s reply).

When a programmer uses inline asm, they’re implicitly telling the compiler that they do know what they’re doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. “cpuid”) or the compiler isn’t able to give them the needed performance in a critical section. I’m extending this sentiment to callbr with output constraints. Let’s take your example below and write it as “normal” asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
br i1 %cmp, label %true, label %false

true:

%0 = call { i32, i32 } asm sideeffect “poetry $0, $1”, “={r8},={r9}” ()

br label %end

false:

%1 = call { i32, i32 } asm sideeffect “poetry2 $0, $1”, “={r10},={r11}” ()
br label %end

end:
%vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever’s done today for “normal” inline asm is what I think should be the behavior for the inline asm callbr variant. If this doesn’t seem sensible (and I realize that I may be thinking of an “in a perfect world” scenario), then we’ll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

This example is no problem, because instructions can be emitted between what’s emitted by “call asm” and the end of the block (be it a fallthrough, or a jump instruction. What gets emitted there is a move of the output register to another location – either a register or to the stack. And therefore at the beginning of the “end” block, “%vals” is always in a consistent location, no matter how you got to that block.

But in the callbr case, there is not a location at which those moves can be emitted, after the callbr, before the jump to “error”.

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how “the programmer knows what they’re doing”. Perhaps I’m being too cavalier here? My concern, if you want to call it that, is that we don’t be too restrictive on the new behavior. For example, the “asm goto” may set a register to an error value (made up on the spot; may not be a common use). But, if there’s no real reason to have the value be valid on the abnormal path, then sure we can declare that it’s not valid on the abnormal path.

I think I should explain my “programmer knows what they’re doing” statement a bit better. I’m specifically referring to inline asm here. The more general “callbr” case may still need to be considered (see Reid’s reply).

When a programmer uses inline asm, they’re implicitly telling the compiler that they do know what they’re doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. “cpuid”) or the compiler isn’t able to give them the needed performance in a critical section. I’m extending this sentiment to callbr with output constraints. Let’s take your example below and write it as “normal” asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
br i1 %cmp, label %true, label %false

true:

%0 = call { i32, i32 } asm sideeffect “poetry $0, $1”, “={r8},={r9}” ()

br label %end

false:

%1 = call { i32, i32 } asm sideeffect “poetry2 $0, $1”, “={r10},={r11}” ()
br label %end

end:
%vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever’s done today for “normal” inline asm is what I think should be the behavior for the inline asm callbr variant. If this doesn’t seem sensible (and I realize that I may be thinking of an “in a perfect world” scenario), then we’ll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

This example is no problem, because instructions can be emitted between what’s emitted by “call asm” and the end of the block (be it a fallthrough, or a jump instruction. What gets emitted there is a move of the output register to another location – either a register or to the stack. And therefore at the beginning of the “end” block, “%vals” is always in a consistent location, no matter how you got to that block.

But in the callbr case, there is not a location at which those moves can be emitted, after the callbr, before the jump to “error”.

I see what you mean. Let’s say we create a pseudo-instruction (similar to landingpad, et al) that needs to be lowered by the backend in a reasonable manner. The EH stuff has an external process/library that performs the actual unwinding and which sets the values accordingly. We won’t have this. What we could do instead is split the edges and insert the copy-to- statements there. So something like:

bb1:

callbr … [label %asm.goto.dest]

bb2:

callbr … [label %asm.goto.dest]

asm.goto.dest:

<<<

converted to something like:

bb1:

callbr … [label %asm.goto.dest.bb1]

bb2:

callbr … [label %asm.goto.dest.bb2]

asm.goto.dest.bb1:

%v.bb1 = extractvalue …

br label %asm.goto.dest

asm.goto.dest.bb2:

%v.bb2 = extractvalue …

br label %asm.goto.dest

asm.goto.dest:

%v = phi [%v.bb1, label %asm.goto.dest.bb1], [%v.bb2, label %asm.goto.bb2]

<<<

It’s not 100% not barfy, but it’s what the compiler does in similar situations.

-bw

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how “the programmer knows what they’re doing”. Perhaps I’m being too cavalier here? My concern, if you want to call it that, is that we don’t be too restrictive on the new behavior. For example, the “asm goto” may set a register to an error value (made up on the spot; may not be a common use). But, if there’s no real reason to have the value be valid on the abnormal path, then sure we can declare that it’s not valid on the abnormal path.

I think I should explain my “programmer knows what they’re doing” statement a bit better. I’m specifically referring to inline asm here. The more general “callbr” case may still need to be considered (see Reid’s reply).

When a programmer uses inline asm, they’re implicitly telling the compiler that they do know what they’re doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. “cpuid”) or the compiler isn’t able to give them the needed performance in a critical section. I’m extending this sentiment to callbr with output constraints. Let’s take your example below and write it as “normal” asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
br i1 %cmp, label %true, label %false

true:

%0 = call { i32, i32 } asm sideeffect “poetry $0, $1”, “={r8},={r9}” ()

br label %end

false:

%1 = call { i32, i32 } asm sideeffect “poetry2 $0, $1”, “={r10},={r11}” ()
br label %end

end:
%vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever’s done today for “normal” inline asm is what I think should be the behavior for the inline asm callbr variant. If this doesn’t seem sensible (and I realize that I may be thinking of an “in a perfect world” scenario), then we’ll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

This example is no problem, because instructions can be emitted between what’s emitted by “call asm” and the end of the block (be it a fallthrough, or a jump instruction. What gets emitted there is a move of the output register to another location – either a register or to the stack. And therefore at the beginning of the “end” block, “%vals” is always in a consistent location, no matter how you got to that block.

But in the callbr case, there is not a location at which those moves can be emitted, after the callbr, before the jump to “error”.

I see what you mean. Let’s say we create a pseudo-instruction (similar to landingpad, et al) that needs to be lowered by the backend in a reasonable manner. The EH stuff has an external process/library that performs the actual unwinding and which sets the values accordingly. We won’t have this.

What we could do instead is split the edges and insert the copy-to- statements there.

Exactly – except that doing that is potentially an invalid transform, because the address is being used as a value, not simply a jump target. The label list is just a list of possible jump targets, changing those won’t actually affect anything. You’d instead need to change the blockaddress constant, but in the general case you don’t know where that address came from – (and it may therefore be required that you have the same address for two separate callbr instructions).

I guess this kinda touches on some of the same issues as in the other discussion about the handling of the blockaddress in callbr and inlining, etc…

I wonder if we could put some validity restrictions on the IR structure, rather than trying to fix things up after the fact by attempting to split blocks. E.g., we could state that it’s invalid to have a phi which uses the value defined by a callbr, if it’s conditioned on that same block as predecessor. That is: it’s valid to use other values defined in the block ending in callbr, because they can be moved prior to the callbr. It’s also valid to use the value defined by the callbr in a phi conditioned on some other intermediate block as predecessor, because then any required moves can happen in the intermediate block.

I believe such an IR restriction should be sufficient to make it possible to emit valid code from the IR in all cases, but I’m a bit afraid of how badly adding such odd edge-cases might screw up the rest of the compiler and optimizer.

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify _different_ constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how "the programmer knows what they're doing". Perhaps I'm being too cavalier here? My concern, if you want to call it that, is that we don't be too restrictive on the new behavior. For example, the "asm goto" may set a register to an error value (made up on the spot; may not be a common use). But, if there's no real reason to have the value be valid on the abnormal path, then sure we can declare that it's not valid on the abnormal path.

I think I should explain my "programmer knows what they're doing" statement a bit better. I'm specifically referring to inline asm here. The more general "callbr" case may still need to be considered (see Reid's reply).

When a programmer uses inline asm, they're implicitly telling the compiler that they *do* know what they're doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. "cpuid") or the compiler isn't able to give them the needed performance in a critical section. I'm extending this sentiment to callbr with output constraints. Let's take your example below and write it as "normal" asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
  br i1 %cmp, label %true, label %false

true:
  %0 = call { i32, i32 } asm sideeffect "poetry $0, $1", "={r8},={r9}" ()
  br label %end

false:
  %1 = call { i32, i32 } asm sideeffect "poetry2 $0, $1", "={r10},={r11}" ()
  br label %end

end:
  %vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever's done today for "normal" inline asm is what I *think* should be the behavior for the inline asm callbr variant. If this doesn't seem sensible (and I realize that I may be thinking of an "in a perfect world" scenario), then we'll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

This example is no problem, because instructions can be emitted between what's emitted by "call asm" and the end of the block (be it a fallthrough, or a jump instruction. What gets emitted there is a move of the output register to another location -- either a register or to the stack. And therefore at the beginning of the "end" block, "%vals" is always in a consistent location, no matter how you got to that block.

But in the callbr case, there is not a location at which those moves can be emitted, after the callbr, before the jump to "error".

I see what you mean. Let's say we create a pseudo-instruction (similar to landingpad, et al) that needs to be lowered by the backend in a reasonable manner. The EH stuff has an external process/library that performs the actual unwinding and which sets the values accordingly. We won't have this.

What we could do instead is split the edges and insert the copy-to-<where ever> statements there.

Exactly -- except that doing that is potentially an invalid transform, because the address is being used as a value, not simply a jump target. The label list is just a list of _possible_ jump targets, changing those won't actually affect anything. You'd instead need to change the blockaddress constant, but in the general case you don't know where that address came from -- (and it may therefore be required that you have the same address for two separate callbr instructions).

I guess this kinda touches on some of the same issues as in the other discussion about the handling of the blockaddress in callbr and inlining, etc...

I wonder if we could put some validity restrictions on the IR structure, rather than trying to fix things up after the fact by attempting to split blocks. E.g., we could state that it's invalid to have a phi which uses the value defined by a callbr, if it's conditioned on that same block as predecessor. That is: it's valid to use _other_ values defined in the block ending in callbr, because they can be moved prior to the callbr. It's also valid to use the value defined by the callbr in a phi conditioned on some other intermediate block as predecessor, because then any required moves can happen in the intermediate block.

I believe such an IR restriction should be sufficient to make it possible to emit valid code from the IR in all cases, but I'm a bit afraid of how badly adding such odd edge-cases might screw up the rest of the compiler and optimizer.

I think that your fear is justified.

In any case, if we're going to support forming this kind of callbr in Clang, then Clang still needs a place to put the stack stores after the inline asm in order to represent the output constraints - which are specified in terms of source-level variables and those are always in stack locations when Clang is generating IR. I think that we can make all of this work if we say that the output constraints, and thus the outputs of the callbr, dominate only uses on the normal "fallthrough" branch. Then the compiler has a single place to put the stores (and, later, a place to put register copies, etc.).

-Hal

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify different constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how “the programmer knows what they’re doing”. Perhaps I’m being too cavalier here? My concern, if you want to call it that, is that we don’t be too restrictive on the new behavior. For example, the “asm goto” may set a register to an error value (made up on the spot; may not be a common use). But, if there’s no real reason to have the value be valid on the abnormal path, then sure we can declare that it’s not valid on the abnormal path.

I think I should explain my “programmer knows what they’re doing” statement a bit better. I’m specifically referring to inline asm here. The more general “callbr” case may still need to be considered (see Reid’s reply).

When a programmer uses inline asm, they’re implicitly telling the compiler that they do know what they’re doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. “cpuid”) or the compiler isn’t able to give them the needed performance in a critical section. I’m extending this sentiment to callbr with output constraints. Let’s take your example below and write it as “normal” asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
br i1 %cmp, label %true, label %false

true:

%0 = call { i32, i32 } asm sideeffect “poetry $0, $1”, “={r8},={r9}” ()

br label %end

false:

%1 = call { i32, i32 } asm sideeffect “poetry2 $0, $1”, “={r10},={r11}” ()
br label %end

end:
%vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever’s done today for “normal” inline asm is what I think should be the behavior for the inline asm callbr variant. If this doesn’t seem sensible (and I realize that I may be thinking of an “in a perfect world” scenario), then we’ll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

This example is no problem, because instructions can be emitted between what’s emitted by “call asm” and the end of the block (be it a fallthrough, or a jump instruction. What gets emitted there is a move of the output register to another location – either a register or to the stack. And therefore at the beginning of the “end” block, “%vals” is always in a consistent location, no matter how you got to that block.

But in the callbr case, there is not a location at which those moves can be emitted, after the callbr, before the jump to “error”.

I see what you mean. Let’s say we create a pseudo-instruction (similar to landingpad, et al) that needs to be lowered by the backend in a reasonable manner. The EH stuff has an external process/library that performs the actual unwinding and which sets the values accordingly. We won’t have this.

What we could do instead is split the edges and insert the copy-to- statements there.

Exactly – except that doing that is potentially an invalid transform, because the address is being used as a value, not simply a jump target. The label list is just a list of possible jump targets, changing those won’t actually affect anything. You’d instead need to change the blockaddress constant, but in the general case you don’t know where that address came from – (and it may therefore be required that you have the same address for two separate callbr instructions).

I guess this kinda touches on some of the same issues as in the other discussion about the handling of the blockaddress in callbr and inlining, etc…

I wonder if we could put some validity restrictions on the IR structure, rather than trying to fix things up after the fact by attempting to split blocks. E.g., we could state that it’s invalid to have a phi which uses the value defined by a callbr, if it’s conditioned on that same block as predecessor. That is: it’s valid to use other values defined in the block ending in callbr, because they can be moved prior to the callbr. It’s also valid to use the value defined by the callbr in a phi conditioned on some other intermediate block as predecessor, because then any required moves can happen in the intermediate block.

I believe such an IR restriction should be sufficient to make it possible to emit valid code from the IR in all cases, but I’m a bit afraid of how badly adding such odd edge-cases might screw up the rest of the compiler and optimizer.

That may be a reasonable restriction to place on the code.

Allow me to wildly speculate a bit. What I would like to have happen is to generate assembly akin to this:

Lasm.goto.dest: ; The original blockaddress destination.

Lasm.goto.dest.bb1:

mov %…, %…

jmp Lasm.goto.dest.body

Lasm.goto.dest.bb2:

mov %…, %…

jmp Lasm.goto.dest.body ; This would be elided, of course.

Lasm.goto.dest.body:

This preserves the blockaddress value. If we create a new instruction, let’s say `indirectval’ (a horrible name, but used for this example), it could save us from having to deal with edge splitting. It could take values similar to a phi node:

= indirectval [%v1, label %bb1], [%v2, label %bb2]

where %v1 and %v2 are from callbr instructions. When we are converting the IR into machine instructions, we can generate something similar to the example above:

asm.goto.dest:

BR asm.goto.dest.bb1

asm.goto.dest.bb1:

MOV …

BR asm.goto.dest.body

asm.goto.dest.bb2:

MOV …

BR asm.goto.dest.body

asm.goto.dest.body:

The one issue is the precise instruction to add to access the values. Perhaps they could be inserted directly before the indirectval inst.

I think that your fear is justified.

In any case, if we’re going to support forming this kind of callbr in Clang, then Clang still needs a place to put the stack stores after the inline asm in order to represent the output constraints - which are specified in terms of source-level variables and those are always in stack locations when Clang is generating IR. I think that we can make all of this work if we say that the output constraints, and thus the outputs of the callbr, dominate only uses on the normal “fallthrough” branch. Then the compiler has a single place to put the stores (and, later, a place to put register copies, etc.).

Hal, Are you saying that values should not be used on indirect branches?

-bw

I think this is fine, except that it stops at the point where things actually start to get interesting and tricky.

How will you actually handle the flow of values from the callbr into the error blocks? A callbr can specify requirements on where its outputs live. So, what if two callbr, in different branches of code, specify _different_ constraints for the same output, and list the same block as a possible error successor? How can the resulting phi be codegened?

This is where I fall back on the statement about how "the programmer knows what they're doing". Perhaps I'm being too cavalier here? My concern, if you want to call it that, is that we don't be too restrictive on the new behavior. For example, the "asm goto" may set a register to an error value (made up on the spot; may not be a common use). But, if there's no real reason to have the value be valid on the abnormal path, then sure we can declare that it's not valid on the abnormal path.

I think I should explain my "programmer knows what they're doing" statement a bit better. I'm specifically referring to inline asm here. The more general "callbr" case may still need to be considered (see Reid's reply).

When a programmer uses inline asm, they're implicitly telling the compiler that they *do* know what they're doing (I know this is common knowledge, but I wanted to reiterate it.). In particular, either they need to reference an instruction not readily available from the compiler (e.g. "cpuid") or the compiler isn't able to give them the needed performance in a critical section. I'm extending this sentiment to callbr with output constraints. Let's take your example below and write it as "normal" asm statements one on each branch of an if-then-else (please ignore any syntax errors):

if:
  br i1 %cmp, label %true, label %false

true:
  %0 = call { i32, i32 } asm sideeffect "poetry $0, $1", "={r8},={r9}" ()
  br label %end

false:
  %1 = call { i32, i32 } asm sideeffect "poetry2 $0, $1", "={r10},={r11}" ()
  br label %end

end:
  %vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]

How is this handled in codegen? Is it an error or does the back-end handle it? Whatever's done today for "normal" inline asm is what I *think* should be the behavior for the inline asm callbr variant. If this doesn't seem sensible (and I realize that I may be thinking of an "in a perfect world" scenario), then we'll need to come up with a more sensible solution which may be to disallow the values on the error block until we can think of a better way to handle them.

This example is no problem, because instructions can be emitted between what's emitted by "call asm" and the end of the block (be it a fallthrough, or a jump instruction. What gets emitted there is a move of the output register to another location -- either a register or to the stack. And therefore at the beginning of the "end" block, "%vals" is always in a consistent location, no matter how you got to that block.

But in the callbr case, there is not a location at which those moves can be emitted, after the callbr, before the jump to "error".

I see what you mean. Let's say we create a pseudo-instruction (similar to landingpad, et al) that needs to be lowered by the backend in a reasonable manner. The EH stuff has an external process/library that performs the actual unwinding and which sets the values accordingly. We won't have this.

What we could do instead is split the edges and insert the copy-to-<where ever> statements there.

Exactly -- except that doing that is potentially an invalid transform, because the address is being used as a value, not simply a jump target. The label list is just a list of _possible_ jump targets, changing those won't actually affect anything. You'd instead need to change the blockaddress constant, but in the general case you don't know where that address came from -- (and it may therefore be required that you have the same address for two separate callbr instructions).

I guess this kinda touches on some of the same issues as in the other discussion about the handling of the blockaddress in callbr and inlining, etc...

I wonder if we could put some validity restrictions on the IR structure, rather than trying to fix things up after the fact by attempting to split blocks. E.g., we could state that it's invalid to have a phi which uses the value defined by a callbr, if it's conditioned on that same block as predecessor. That is: it's valid to use _other_ values defined in the block ending in callbr, because they can be moved prior to the callbr. It's also valid to use the value defined by the callbr in a phi conditioned on some other intermediate block as predecessor, because then any required moves can happen in the intermediate block.

I believe such an IR restriction should be sufficient to make it possible to emit valid code from the IR in all cases, but I'm a bit afraid of how badly adding such odd edge-cases might screw up the rest of the compiler and optimizer.
That may be a reasonable restriction to place on the code.

Allow me to wildly speculate a bit. What I would like to have happen is to generate assembly akin to this:

Lasm.goto.dest: ; The original blockaddress destination.

Lasm.goto.dest.bb1:

  mov %..., %...

  jmp Lasm.goto.dest.body

Lasm.goto.dest.bb2:

  mov %..., %...

  jmp Lasm.goto.dest.body ; This would be elided, of course.

Lasm.goto.dest.body:

  ...

This preserves the blockaddress value. If we create a new instruction, let's say `indirectval' (a horrible name, but used for this example), it could save us from having to deal with edge splitting. It could take values similar to a phi node:

  <val> = indirectval <ty> [%v1, label %bb1], [%v2, label %bb2]

where %v1 and %v2 are from callbr instructions. When we are converting the IR into machine instructions, we can generate something similar to the example above:

asm.goto.dest:

  BR asm.goto.dest.bb1

asm.goto.dest.bb1:

  MOV ...

  BR asm.goto.dest.body

asm.goto.dest.bb2:

  MOV ...

  BR asm.goto.dest.body

asm.goto.dest.body:

  ...

The one issue is the precise instruction to add to access the values. Perhaps they could be inserted directly before the indirectval inst.

I don't understand how you can perform the renaming in general. Can't the block address to which the code jumps be provided as a pointer value (presumably generated using the labels-as-values extension)?

I think that your fear is justified.

In any case, if we're going to support forming this kind of callbr in Clang, then Clang still needs a place to put the stack stores after the inline asm in order to represent the output constraints - which are specified in terms of source-level variables and those are always in stack locations when Clang is generating IR. I think that we can make all of this work if we say that the output constraints, and thus the outputs of the callbr, dominate only uses on the normal "fallthrough" branch. Then the compiler has a single place to put the stores (and, later, a place to put register copies, etc.).

Hal, Are you saying that values should not be used on indirect branches?

Yes.

-Hal

-bw