[RFC] [LV] Introducing VPlan to model the vectorized code and drive its transformation

Hi All,

This is an RFC for the design of VPlan following our original RFC[1], Dev Meeting presentation[2], and the patch posted for high-level review[3]. To recap, the proposal involves introducing a Vectorization Plan as an explicit model of a vectorization candidate and update the flow of the innermost Loop Vectorizer accordingly.

The patch[3] is designed to show key aspects of the VPlan model, demonstrating how it can capture precisely all vectorization decisions taken inside a to-be vectorized loop by the current Loop Vectorizer, and carry them out. It is therefore practically a “No Change in Output intended” patch. The technical details are documented in the patch which includes an rst file and a pdf attached to the review on https://reviews.llvm.org/D28975#655369.

Comments are most welcome, here and/or on Phabricator.

Gil and Ayal.

[1] [llvm-dev] RFC: Extending LV to vectorize outerloops, http://lists.llvm.org/pipermail/llvm-dev/2016-September/105057.html

[2] Extending LoopVectorizer towards supporting OpenMP4.5 SIMD and outer loop auto-vectorization, 2016 LLVM Developers’ Meeting, https://www.youtube.com/watch?v=XXAvdUwO7kQ

[3] Patch titled “[LV] Introducing VPlan to model the vectorized code and drive its transformation” posted for review on https://reviews.llvm.org/D28975.