I recently had a bug report on the RISC-V backend that Rust’s
compiler_fence (which generates the same IR as C/C++'s
atomic_signal_fence) was emitting machine code when it didn’t need to.
Most targets seem to handle this the same way, in that they introduce a custom node (often called MEMBARRIER) that expands to an assembly comment, in order to implement this. I could have done the same for RISC-V, but it felt a bit like we were copy/pasting what other backends do.
Instead, I prepared a patch which adds a TargetOpcode::COMPILER_BARRIER, to be used as a target-independent compiler barrier, which just expands to an assembly comment (but no instructions). I’ve tried to implement this in a way that allows backends with more complex memory models to avoid introducing no instructions where that would be incorrect (for instance, AMDGPU has more complex requirements on what syncscope::singlethread means).
I have prepared a patch, here: https://reviews.llvm.org/D92842
This patch adds the feature, and moves the RISC-V, x86, Arm and AArch64 backends to use this feature, instead of their target-specific equivalents.
I would welcome feedback on the approach in the patch, or any concerns you have about this approach.
Thanks in advance,