RISC-V (bare-board) debugging?

Subprojects LLDB
1

I saw the impending patch https://reviews.llvm.org/D62732, which suggests that the current LLDB doesn’t support RISC-V targets at all? If that’s correct, then do I understand correctly that the patch will support bare-board debugging, e.g. via openocd?

Is there any sentiment on when the patch will land?

(background being that so far we’ve been using gdb + openocd to debug LLVM-built images running on a VexRiscV platform, but obviously would prefer to be purely-LLVM)

Cheers,
Tom

2

I saw the impending patch https://reviews.llvm.org/D62732, which suggests that the current LLDB doesn’t support RISC-V targets at all? If that’s correct, then do I understand correctly that the patch will support bare-board debugging, e.g. via openocd?

We have some people debugging using this patch and a RISC-V simulator, so this does work.

Is there any sentiment on when the patch will land?

I believe testing is the main thing holding this patch up right now. I would like to see this resolved and checked in. We might need a built that can add support for RISC-V so that we can test the functionality.