[RISC-V] Consult the command to compile RISC-V "V" Extension by inline assembly

Hello all,

I meet a error when compile RISC-V RVV inline assembly, by the llvm which I built from master’s source code. It can work by riscv-gnu-toolchain which I built from rvv-intrinsic branch.

I want to consult here about RISC-V “V” Extension in LLVM. Maybe I use the wrong command, or RVV inline assembly has not been supported in master (something like a special branch like riscv-gnu-gcc)?


Best Regards
Pan Yong

Below is the basic information about my issue:

Source Code:

int main()
    int vl;
    int size = 1024;
    asm volatile("vsetvli %0, %1," "e32" "," "m4" : "=r" (vl) : "r" (size));
    asm volatile("vadd.vv" " " "v8" ", " "v0" ", " "v4");
    return 0;

clang --sysroot=./riscv/riscv64-unknown-elf --gcc-toolchain=./riscv -march=rv64gv0p10 -menable-experimental-extensions rvv_test.c -o rvv_test


rvv_test.c:5:18: error: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
      asm volatile("vsetvli %0, %1," "e32" "," "m4" : "=r" (vl) : "r" (size));

<inline asm>:1:17: note: instantiated into assembly here
              vsetvli a1, a1,e32,m4

1 error generated.


After checking the source code of LLVM, I think I have found the root cause of my issue.

In RISCVAsmParser.cpp,

OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
... ...
  if (VTypeIElements.size() == 7) {
... ...

// If NoMatch, unlex all the tokens that comprise a vtypei operand


  while (!VTypeIElements.empty())


  return MatchOperand_NoMatch;


So it means I need to use the full instruction as below,
vsetvli a1, t0, e8, m8, ta, ma
But cannot use the simplified instruction as below,
vsetvli a1, a1,e32,m4

After I change to the full instruction with 6 operands, this issue has been resolved.

Best Regards
Pan Yong