RISC-V LLVM sync-up call 14th May 2020

For background on these calls, see

Reminder: the purpose is to co-ordinate between active contributors.
If you have support questions etc then it's best to post to llvm-dev.

We have a call each Thursday at 4pm BST, via

I've created a shared calendar which may help in keeping track, which
is accessible at:
  * <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ&gt;
  * <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics&gt;

Issues to discuss today include the following:

* Upcoming 10.0.1-rc1 branch
* Bitmanip split patches up for review (now split to
⚙ D79870 [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions and others)
* Recent ABI bug for complex floats ⚙ D79770 [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64 -
what is the usual approach for dealing with ABI bug fixes?
* Any more RVV RFC feedback
[llvm-dev] [RFC] RISC-V Vector Intrinsics
* Also worth noting: the fix for folding of addi of constant pool
load/stores landed, which is a really nice improvement for workloads
using the F and D extension in particular he fix for folding of addi
of constant pool load/stores landed ⚙ D79689 [RISCV][NFC] Add tests for folds of ADDIs into load/stores
* No other topics were submitted, as always, please do submit things
you'd like to discuss