RISC-V LLVM sync-up call 14th Nov 2019

For background on these calls, see

Reminder: the purpose is to co-ordinate between active contributors.
If you have support questions etc then it's best to post to llvm-dev.

We have a call each Thursday at 4pm GMT, via

I've created a shared calendar which may help in keeping track, which
is hopefully accessible at:
  * <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ&gt;
  * <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics&gt;

Issues to discuss today include the following:
* Infinite loop in TableGen. Apparently only shows up for RISC-V,
though feels likely we're victim of an obscure miscompile
⚙ D69741 [Codegen] Both sides of '&&' are same; fixed - does anyone have time to help out
* Flagging up for extra review: R_RISCV_32_PCREL
<Login, re-opened CFI directive fix
* R_RISCV_SET6 semantics?
* Sam is working on ilp32e codegen
* The patch to use compiler-rt has seen a lot of activity recently
⚙ D68407 [RISCV] Use compiler-rt if no GCC installation detected
* I think we're about ready to land the march/mabi change D69383
* In-flight patches of note:
  * GlobalISel return lowering ⚙ D69808 [RISCV GlobalISel] Add lowerReturn for calling conv. awaiting review
  * V extension MC layer patch ⚙ D69987 [RISCV] Assemble/Disassemble v-ext instructions.