RISC-V LLVM sync-up call 18th March 2021 (*Note* US daylight savings time)

*Note*: The US recently entered daylight savings time, but we haven't
done so in Europe yet. This meeting is still at 4pm GMT - but may be
an hour later than you're used to if you've entered DST already. We'll
discuss timing for the next meeting today.

For background on these calls, see

Reminder: the purpose is to co-ordinate between active contributors.
If you have support questions etc then it's best to post to llvm-dev.

We have a call every alternate Thursday at 4pm GMT, via
<https://meet.google.com/ske-zcog-spp&gt;\. If you have topics to discuss,
please email me ahead and I can add them to the agenda.

We have a shared calendar which may help in keeping track, which is
accessible at:
* <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ&gt;
* <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics&gt;

* Patches or bugs to note / briefly discuss:
  * LLVM is gaining documentation on the recurring sync-ups
  * Reported bug in V support - feels too late for 12.0.0 at this point?
    <49623 – [RISCV] Wrong operand order in ISEL pattern for masked vmslt[u];
  * Parsing multi-lib config from GCC <Login;
  * Search FilePaths for compiler-rt before falling back
  * 'v' inline asm constraint <Login;
  * Enabling VIU75 and vector support <Login;
  * LocalStackSlotAllocation <https://reviews.llvm.org/D98101&gt;
* Integer materialisation: <https://reviews.llvm.org/D98821&gt; and whether we
  should route all materialisation through selectImm
* RFC: Support of non-default floating point environment on RISC-V
* Passing 'half' in the lower 16 bits of an f32 value
* RFC: `__fp16` on RISC-V
* Load/store/alloca for structs with all the same scalable vectors
  <Login; - anything this group can do to help
  progress this discussion?
* Time and date of next meeting