RISC-V LLVM sync-up call 5th Dec 2019

For background on these calls, see

Reminder: the purpose is to co-ordinate between active contributors.
If you have support questions etc then it's best to post to llvm-dev.

We have a call each Thursday at 4pm GMT, via

I've created a shared calendar which may help in keeping track, which
is hopefully accessible at:
  * <https://calendar.google.com/calendar/b/1?cid=bG93cmlzYy5vcmdfMG41cGtlc2ZqY25wMGJoNWhwczFwMGJkODBAZ3JvdXAuY2FsZW5kYXIuZ29vZ2xlLmNvbQ>
  * <https://calendar.google.com/calendar/ical/lowrisc.org_0n5pkesfjcnp0bh5hps1p0bd80%40group.calendar.google.com/public/basic.ics>

Issues to discuss today include the following:
* Luis has posted a patch to test the resolving of RISC-V relocations
(https://reviews.llvm.org/D70541). There were some concerns that the
patch relied too much on binary blobs. The patch was updated to have a
corresponding assembly representation where possible. There is still
some discussion about whether the whole test should be converted to
* Ana's patch to better estimate instruction size for compressed
instructions (https://reviews.llvm.org/D68290) is ready for review.
This patch is used by the machine outliner patch.
* The Rocket scheduler model patch (https://reviews.llvm.org/D68685)
was updated after the last call. A few more review comments were added
after that.
* We may want to discuss <https://reviews.llvm.org/D70116> related to LTO
* The canRealignStack needs a different approach
<https://reviews.llvm.org/D70670> - Sam aims to return to this