Selection DAG node for 64-bit load

Hi Fellow LLVM Experts,

Currently, Selection DAG node for load seems to expect a 32-bit base and an offset. Is it possible to extend load node definition to 2 32-bit bases and an offset? Two 32-bit bases are supposed to represent one 64-bit address.

Any suggestions, comments are much appreciated.

Regards,

Iftekhar

From: "Iftekhar Chowdhury" <iftekhar.hc@gmail.com>
To: llvmdev@cs.uiuc.edu
Sent: Tuesday, July 8, 2014 1:06:44 PM
Subject: [LLVMdev] Selection DAG node for 64-bit load

Hi Fellow LLVM Experts,

Currently, Selection DAG node for load seems to expect a 32-bit base
and an offset. Is it possible to extend load node definition to 2
32-bit bases and an offset? Two 32-bit bases are supposed to
represent one 64-bit address.

I don't understand why you're suggesting this? Does your target have a 64-bit address space but no 64-bit GPRs?

-Hal

Yes, the target does not have 64-bit GPRs. But it still needs to support 64-bit address space.

Cheers,
Iftekhar

Hi

Do the two 32-bit bases need to be stored in consecutive registers? If
so, you could still use the 64-bit loads and then use REQ_SEQUENCE to create
a pair of 32-bit registers.

-Tom

Hi Tom,

Thanks for getting back to me. Let me elaborate on my problem a bit.

Currently, Selection DAG generates the following for stack load / store when needed:

LOAD <FrameIndex #0>, 0, … ; 0 = offset

I would like to change the above to:

LOAD <FrameIndex #0>, %Dummy_GPR, 0, …

The Dummy_GPR is used for 32-bit pointers, which will be ignored by later passes. The idea is to have a single instruction format for both 32-bit and 64-bit load / store.

I have already modifed TD to reflect instruction format changes.

I am currently hitting an assertion in InstrEmitter::EmitMachineNode due to mismatch between TD definition and SDNode definition.

I’m not quite sure how to go about changing SDNode definition for LOAD to reflect TD changes.

Any suggestions are much appreciated.

Regards,
Iftekhar