SelectionDAG Preserves IR Order

I want to make folks aware of Xiaoyi's fixes to SelectionDAG. They ensure that all SelectionDAG nodes, except for constants and such, are assigned an order which is propagated through the SD passes. This fixes the problem of debug information being dropped by SelectionDAG. I'm particularly happy because it means that -pre-RA-sched=source now works the way it was meant to. This means I can effectively bypass the SelectionDAG scheduler and enable the MachineScheduler. Otherwise MachineScheduler would have to correct any havoc wrought by SD scheduler, which it is not designed to do.

I committed Xiaoyi's patches as: r182701,r182703,r182704,182706.

Beware that out-of-tree targets will see merge conflicts in <Tgt>ISelDAGToDAG.cpp and <Tgt>ISelLowering.cpp. These should be trivial to resolve with a regex replace something like this:

's/DebugLoc dl = ([^.]+)\.getNode\(\)->getDebugLoc\(\)/SDLoc dl(\1)/g'