I'm pretty new to the community, but I've run into a number of
questions while building a backend for a custom target. I'll keep it
to one topic per thread, though.
My target has arithmetic instructions (add, sub, etc...) which all set
the flags register. There is no explicit comparison instruction for my
target. The conditional branching instructions check the flags
This is not so different from a number of other platforms (e.g. X86,
ARM), which have arithmetic instructions which set flags. So I looked
at the backend implementations for those platforms. The ARM conditions
seem to sorta-kinda use predicated instructions (the subject of my
next mail). The x86 implementation seems closer to what I want.
On closer inspection though, it turns out that the x86 implementation
ALWAYS emits a new comparison instruction (in LowerBRCOND and
LowerSELECT). baldrick encouraged me to submit bug #3761
(http://llvm.org/bugs/show_bug.cgi?id=3761) as this is suboptimal.
My question is how do I achieve my goal? How do I get llvm to
recognize the fact that my ALU instructions set the flag register?
Thanks for your help,