From what I can tell the MinVLEN is being set to 128 for all RISCV targets. Should this be changed to be set by subtarget?
I thought it follows the Zvl*b extension from -march. And -mcpu should imply -march.
So the default is 128b unless Zvl*b feature is supported? Ok, thanks.
@topperc Another question, is this a naming convention? VLEN is the physical register vector width in bits? It’s not clear why VLEN is needed so much as LMUL and vector length? Am I misunderstanding something here?