Some reflexions about a new HDL language


I am thinking about making a compiler for a new HDL language, that will be more modern than VHDL and Verilog and allow a little higher level behavioral description than VHDL. For this language, I am beeing influenced by VHDL, Ada, Ruby and MyHDL. I also would like to write it in Ada.
I don’t know if it is a project that I will abandon as fast as it popped up in my mind, or not . Anyways, here are my primilary reflexions for this new language : What are your feedbacks ? PS : Next week, I will be on vacation for 3 mounths, so I may have irregular access to the internet. Cheers, Jonas