Eli,

I have a simple SplitVecRes function that implements what you mentioned, splitting the LHS just as in BinaryOp, but passing through the RHS. The problem is that the second operand is MVT::Other, but when casted to an VTSDNode reveals that it is a vector length of the same size as the LHS SDValue. This causes a split on the LHS side to work correctly, but then it fails instruction selection because of Other. I have not been able to figure out how to split the MVT::Other node yet, any idea how to do this?

Instruction selection fails because it cannot match the pattern:

v4i8 = sign_extend_inreg <v4i8 node>, <Other node(v8i8 VTSDNode)>

The reason being my initial implementation based on the advice given takes as input:

v8i8 = sign_extend_inreg <v8i8 node>, <Other node(v8i8 VTSDNode)>

and generates two:

v4i8 = sign_extend_inreg <v4i8 node>, <Other node(v8i8 VTSDNode)>

Instead it should generate:

v4i8 = sign_extend_inreg <v4i8 node>, <Other node(v4i8 VTSDNode)>

So, how would I be able to split the Other node so that it will match the resulting data type?

My function looks like this:

void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo,

SDValue &Hi) {

SDValue LHSLo, LHSHi;

GetSplitVector(N->getOperand(0), LHSLo, LHSHi);

SDValue RHS = N->getOperand(1);

DebugLoc dl = N->getDebugLoc();

Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHS);

Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHS);

}

Thanks,

Micah