stack alignment restriction

Project Infrastructure LLVM Dev List Archives
1

Hi
   Is there a way to enforce a different alignment on vales on stack
as compared to other basic types. Particularly, i would like
characters to be stored at 2 byte boundary.

thanks
dz

2

Check out examples in the lib/Target/* directories. For instance in X86CallingConv.td, we have things like this:

def CC_X86_64_C : CallingConv<[
...
  // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
  CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>>
}

The second parameter to CCAssigneToStack is the alignment for that type.

-bw

3

Thanks for the answer..
A followup question - Is this already taken into consideration when
generating address calculation offset etc or would this need to be
specially taken care?
I am assuming all load/stores also would need to be custom lowered.

thanks
dz

4

Thanks for the answer..
A followup question - Is this already taken into consideration when
generating address calculation offset etc or would this need to be
specially taken care?

I believe it should be.

-bw