Steps to implement codegen for a new target (newbie question)


I want to roughly figure out the steps/modules to implement a codegen for a new architecture (like a high level design doc). I also need to do a rough estimation of how much time would be needed to implement each module, this may be not easy. Any pointers/references would be highly appreciated.


Maybe the following links help you:

And the first commit of the new PowerPC GlobalISel port:

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Thanks a lot tschuett!

GlobelISel is the new instruction selector. You still need to define your registers, instructions, …
The link in the middle gives you some ideas.

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Great tschuett, after implementing the skeleton for GlobalISel Skeleton for one instruction (ret void) as seen in ⚙ D83100 [PPC][GlobalISel] Add initial GlobalIsel infrastructure, what are the next steps. I see and files in your skeleton. Wondering when to implement other td files and in what order. Ideally, I would like to implement one instruction at a time but even to do that, it looks like we need all the td files in place. Thanks a lot. Your skeleton link is very useful!

The Link above “Writing an LLVM Backend” should guide you in which tds you have to write.
e.g. AARCH64

Another PowerPC Diff:

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