SUBREG_TO_REG pseudo instruction. Could the immediate operand be of type MO_CImmediate?

From llvm/Support/TargetOpcodes.def, the comment of SUBREG_TO_REG says

/// SUBREG_TO_REG - Assert the value of bits in a super register.
/// The result of this instruction is the value of the second operand inserted
/// into the subregister specified by the third operand. All other bits are
/// assumed to be equal to the bits in the immediate integer constant in the
/// first operand. This instruction just communicates information; No code
/// should be generated.
/// This is typically used after an instruction where the write to a subregister
/// implicitly cleared the bits in the super registers.

When adding some handling for SUBREG_TO_REG instruction, I want to add some assertions like

// SUBREG_TO_REG_MI is known to be a SUBREG_TO_REG instruction.

MachineOperand MO1 = SUBREG_TO_REG_MI.getOperand(1);
 // What about CImm?
  assert((MO1.isImm()) && "MO1 expected to be immediate number");

So I begin to wonder if it’s a valid case that MO1 is of type MO_CImmediate.

The answer is not obvious (to me) from the (following) definition of SUBREG_TO_REG

def SUBREG_TO_REG : StandardPseudoInstruction {
  let OutOperandList = (outs unknown:$dst);
  let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
  let AsmString = "";
  let hasSideEffects = false;
}

Please advise what I miss, thanks so much!

While the definition of SUBREG_TO_REG doesn’t mention the answer, I think the usage of SUBREG_TO_REG in td file under lvm-project/llvm/lib/Target/X86/ would tell how SUBREG_TO_REG is generated and used.