I would like to know how to model an instruction waiting a pipeline unit to be empty for cycles.
For example, I have a vstr that waits FP pipelines to be empty for at most 3 cycles. I set FP instructions use a resource unit called FPPipe with resourceCycle=3 and vstr use FPPipe with resourceClycle=0. So scheduler will know a vstr will wait 3 cycle if it is scheduled right after a FP instruction.
However, this way will cause one FP instruction waits other FP instruction for 3 cycle.
Machine Resource model doesn’t seem to support resource usage advanced in cycles, nor have custom logic for scheduler in c codes.
Is there other suggestion? Any will be helpful.
Thanks in advance.