I've been working on adding support for the PPC 440/450 "embedded" cores
to the PowerPC backend. These are used on IBM's Blue Gene L and P
supercomputers, but are also used in other environments (like on the
Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I
apologize if this is the wrong way to do this [the online docs seem to
imply that a patch should be sent to a mailing list, although does not
specify which one, should it go to the bug tracker instead?].
I've tried to touch as little of the existing code as possible. There
are some other changes which should probably be made, but would require
touching the existing PowerPC code. For example, the general load/store
itinerary should really be split into a general load and general store.
Also, on the so-called "Book E" embedded PPC cores, the sync instruction
is called msync (same opcode, different name). I'm not sure what the
best way of doing a predicate-base asm name is.
I'm just about done with a patch to add support for the FP2 (aka Double
Hummer) v2f64 vector instruction set, but I figured that it would be
good to make that a separate patch.
Thanks in advance,
Hal
llvm_ppc440_20111004.diff (32 KB)
I've been working on adding support for the PPC 440/450 "embedded" cores
to the PowerPC backend. These are used on IBM's Blue Gene L and P
supercomputers, but are also used in other environments (like on the
Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I
apologize if this is the wrong way to do this [the online docs seem to
imply that a patch should be sent to a mailing list, although does not
specify which one, should it go to the bug tracker instead?].
llvm-commits is the place to send your patches.
I've tried to touch as little of the existing code as possible. There
are some other changes which should probably be made, but would require
touching the existing PowerPC code.
This patch looks fine to me, but I am missing some test cases.
There should at least be a test case just sending some code through this scheduler.
For example, the general load/store
itinerary should really be split into a general load and general store.
Also, on the so-called "Book E" embedded PPC cores, the sync instruction
is called msync (same opcode, different name). I'm not sure what the
best way of doing a predicate-base asm name is.
I am not sure how to do that. X86 has alternative syntaxes, but that is way overkill.
I'm just about done with a patch to add support for the FP2 (aka Double
Hummer) v2f64 vector instruction set, but I figured that it would be
good to make that a separate patch.
Definitely.
/jakob
I've been working on adding support for the PPC 440/450 "embedded" cores
to the PowerPC backend. These are used on IBM's Blue Gene L and P
supercomputers, but are also used in other environments (like on the
Xilinx Virtex-5). Here is my first patch. I'm new to LLVM, and so I
apologize if this is the wrong way to do this [the online docs seem to
imply that a patch should be sent to a mailing list, although does not
specify which one, should it go to the bug tracker instead?].
llvm-commits is the place to send your patches.
I've tried to touch as little of the existing code as possible. There
are some other changes which should probably be made, but would require
touching the existing PowerPC code.
This patch looks fine to me, but I am missing some test cases.
There should at least be a test case just sending some code through this scheduler.
For example, the general load/store
itinerary should really be split into a general load and general store.
Also, on the so-called "Book E" embedded PPC cores, the sync instruction
is called msync (same opcode, different name). I'm not sure what the
best way of doing a predicate-base asm name is.
I am not sure how to do that. X86 has alternative syntaxes, but that is way overkill.
You can put a predicate on an InstAlias or a MnemonicAlias. Just do:
def : MnemonicAlias<"msync", "sync">, Requires<[IsBookE]>;
I've attached the latest version of my patch to support the PPC 440/450
cores in the PowerPC backend.
I've also included a small patch to clang so that it will recognize
-target-cpu 440 and pass that through to the code generator (and
assembler).
Thanks in advance,
Hal
llvm_ppc440-20111010.diff (41.6 KB)
clang_ppc440-20111010.diff (2.99 KB)