Support of itineraries and SchedModel in LLVM schedulers

Hello! I have been gathering information by browsing the source code about how each scheduler interacts with the (legacy) itineraries and (newer) SchedModel, in the context of an in-order processor.

I have found the following for latencies:

  • all schedulers (ScheduleDAG, MachineScheduler, PostRASchedulerList) use TargetSchedModel::computeOperandLatency, which abstracts away whether itineraries or schedmodel was used. It seems to take itineraries in priority, so if you have a backend with both present, the itineraries will take precedence. This is for data (Read-After-Write) dependencies.
  • The output latency (in case of Write-After-Write dependencies) seems to be 1 regardless. The TargetSchedModel::computeOutputLatency function returns 1 when the target is in-order. This is only relevant for postRA schedulers, as before register allocation there is no reuse. Similarly, anti dependencies (Write-After-Read) have a latency of 0, as expected.

In terms of resource tracking, there seems to be a little less support:

  • MachineScheduler handles both itineraries and SchedModel conjunctively (if either hazard recognition says “no”, then it’s “no”)
  • PostRATDList and ScheduleDAG only use itineraries for this. If no itinerary is present, there will not be any hazard recognition.

To those who are familiar with scheduling in LLVM, do the above statements look correct to you? I would like to make sure that I have not missed anything there.

Thank you!