I’m wondering if LLVM plans to support paired register constraints for 64-bit data.
Take ARM for example, the atomic i64 value read/write instuctions: ldrexd/strexd, require aligned register pairs (even/odd).
Currently, in LLVM ARM (ARMISelDAGToDAG.cpp), ldrexd/strexd get hard coded registers (R0,R1) before register allocation via intrinsic.
It would be neater if there is a register constraint and register class that support 64-bit data and let the reg allocator to select the available register pair.
More importantly, it can solve issues for inline asm that requires 64-bit data binding: inline asm won’t be treated as intrinsic so there is no guarantee to get paired registers.