Sv.reg names

Hi there!

I am looking to remove registers from a design, the names of which are strings specified by the user. Specifically I want to perform a string comparison between two register names (as they appear in SV or Chisel).

for example by taking the verilogName attribute:
%x = sv.reg {hw.verilogName = "x"} : !hw.inout<i16>

I noticed with a different design however (after lowering by hand with firtool) that this attribute is not always present:
%counter = sv.reg : !hw.inout<i2>

Is there a way to ensure that the verilogName attr is always added ? or can I extract counter in a different, but still reliable way (such as using print with stringstream ? )

Thanks in advance :slight_smile:

hw.verilogName = "x" is an artifact of Verilog Emission so the attribute can be seen only after emission (specifically ExportVerilog pass). firtool foo.fir -output-final-mlir=foo.mlir should dump a final mlir file so you can inspect signal names with your own pass.

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Thanks! much appreciated :slight_smile:

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What Hideto mentioned is the right approach if you need the final name of the register as it was emitted.

Depending on what point in the pipeline you’re interested in, you can also get the name from something like this in a straightforward way:

There should be a name attribute on the operation, set to "counter". CIRCT has implemented the interface to customize the SSA value name to use that attribute in the printed IR. But you don’t need to print the SSA value to get the name, you can just ask for the name attribute. This may not be the final name in the output, because ExportVerilog might rename it to avoid conflicts, etc. But that is another way to get the name earlier in the pipeline, if you care about that use case.

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Yes! I am indeed more interested in earlier parts of the pipeline. I have changed my code to call .getNameAttr() and seems to work :smiley: Thank you again for your help

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