Symbols for wires, regs, and instances

As mentioned in the weekly CIRCT meeting, I have been looking at adding optional symbols to wires, regs, and instances. This change is intended to model two things:

  1. These names are externally visible, and thus form an interface which we must respect during transformation. We don’t, however, want to constrain transforms when these names are an artifact of representation and not part of the interface. The existence of a symbol tied to one of these entities serves as a flag that the entity is public and it and its behavior should be preserved.
  2. Anchor points for Verilog constructs in the IR which can name remote entities. Bind and cross module references are the first two such constructs I know of.

A longer discussion is in the updated rational doc in the PR showing this: Attach symbols to instances, wires, and regs. by darthscsi · Pull Request #1044 · llvm/circt · GitHub

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+1 from me. I mentioned being in favor of this in the context of sv.wire visibility a while back.

Just saw this. FWIW, We’ve come to a point where using Symbols for component (i.e. Module) instances may be useful here.