A requirement for ESI is the ability to integrate deeply with existing SV code. Like be able to produce a SystemVerilog fragment to be `included in some SV code. ESI would have to be able to reason about modules already instantiated in the SystemVerilog and connect up to their ports.
I was thinking of adding two Ops: a region called
fragment and one called
externModule. The former to indicate that this region will become a SV fragment. Presumably, this will signal to whatever is writing the SV that the module/endmodule are to be skipped. The latter is to reason about the necessary properties of an already-instantiated module in the existing SV code. In particular, it would contain ESI ports which the module has as arguments and results.
Does this make sense? If so, in which dialect should it go? It could go in ESI but this seems more general than just ESI.