SystemVerilog style and code formatter?

Though I don’t expect there to be much hand-written SV in CIRCT, should we adopt a standard style? I see a few sv formatting tools out there. Does anyone have any experience with them?

I tried the only OSS code formatter I could find (GitHub - thomasrussellmurphy/istyle-verilog-formatter: Open source implementation of a Verilog formatter) and found it lacking for SystemVerilog.