TableGen: Apart from registers, do we also model internal memory?

While working on developing an LLVM backend for an accelerator architecture, I am faced with a confusion, when the architecture has programmable registers, we model those in the However, if the architecture makes excessive use of an internal memory structure apart from few programmable registers, how do we model them? Rather, is there a specific file to model them?

(The compiler stack I am trying to make will be a cross-compiler.)

There’s mayLoad=1 and/or mayStore=1, and you may attach an appropriate memory operand. There’s also always the catch-all fallback of hasSideEffects for anything unmodeled

Could you please point me to any example?

It depends what produces these instruction references and it depends exactly what the nature of this internal memory is. If it’s a special intrinsic, you can construct a custom PseudoSourceValue and use it in getTgtMemIntrinsic

Not sure, but, it seems to me that this sub-project (MDL) is designed for problems similar to the ones I am facing. I will explore this.