Tablegen definition question

Hi All,

In ARMInstFormats.td predicate is defined this way:

def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),

(ops (i32 14), (i32 zero_reg))> {…}

I use the same definition in my code. But I have another version of predicate which is exactly the same but it is a condition code plus a quantifier! (e.g. Xpred = (pred + i32imm)).

I was wondering how we can define a sub sub operand, something like this:

def Xpred : PredicateOperand<OtherVT, (ops pred, i32imm),

(ops (i32 14), (i32 zero_reg))> {…}

I don’t know how clear I explained, but can someone recommend a solution?

Cheers,

ES

Hi,

You can’t nest operands like that - it must be a flattened list. So:

def Xpred : PredicateOperand<OtherVT, (ops i32imm, i32imm, i32imm),

(ops (i32 14), (i32 zero_reg))> {…}

Hello James,

that was also what I’ve planned to do but just wasn’t sure. Thanks for that.

But one question!

imagine I define cond as a type of Xpred (Xpred:$cond)

and in the instruction, for instance bits<6> cond.

How can I assign the first i32imm to the 4 MSB of cond and the second i32imm to the 2 LSB? :-/

Now:

Xpred:$cond
bits<6> cond;

Inst{5-0} = cond;

Desired:

Xpred:$cond;

bits<6> cond;

Inst{5-2} = cond.ops[0];

Inst{1-0} = cond.ops[1];

Hi,

That’s what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer:

def CondCodeOperand : AsmOperandClass { let Name = “CondCode”; }
def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm),
(ops (i32 14), (i32 zero_reg))> {
let PrintMethod = “printPredicateOperand”;
let ParserMatchClass = CondCodeOperand;
let DecoderMethod = “DecodePredicateOperand”;
}

James

Hello James,

It was actually EncoderMethod.

I implemented the function that uses this logic (borrowed from ARM) and it works. Thanks again for your help :slight_smile:

const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);

Glad it worked!