Tablegen: frameindex matches register


In my backend I have following definition:

def StoreStackR : MyInst<2, (outs), (ins IntRegs:$addr, IntRegs:$reg),
“store $reg, [$addr]”, [(store i32:$reg, frameindex:$addr)]>;

However, LLVM generates both

storestackr %reg1, [%reg2]


storestackr %reg1, [123123]

using this definition. I was expecting that “IntRegs:$addr” would constrain it to registers only. As consequence, I can’t infer operand type from the opcode. What’s the proper way to solve this?

Thanks in advance.

There is no way to match frameindex in TableGen (unless something has changed recently). Use ComplexPattern instead. We do that on Hexagon, grep for AddrFI.