TableGen how to define 64bit immediate pat?

I only have:
def D3 : Rd< 6, “F6”, [F6, F7]>, DwarfRegNum<[75]>;//register pair
movgl reg imm16;//move 16bits to register low16 bits
movgh reg imm16;//move 16bits to register high 16 bits
I don’t kmow how to def Pat for 64bit.


1.I have try use Pseudo instruction in POST-RA, but I don’t know how to get D3’s sub register F6.
2.I want to def pat that match it but It’s too complex to def : Pat use movgl and movgh. immediate is f64 and I have to save it in register pair like D3.
IS there any method to solve it?

After regalloc, you should be able to look up a subreg for a register using TargetRegisterInfo::getSubReg. Or depending on how your registers are defined, you might be able to just do some math, e.g. MyTarget::F0 + 2 * (Reg - MyTarget::D0).

Before regalloc (for example, in a pattern), you can use REG_SEQUENCE to merge two “F” registers into a “D” register.

finally, I use 32bit immediate pat, use load64 and store64.
I’ll check code…